Job Information
Hardware Signal Integrity Engineer
In-TAC Jay Ottawa, Canada 28 Days Ago
Job Category: Computer/IT
Job Type: Full-Time
Posted: 2019-05-28
Minimum Experience: 3 Year
Job Status
No of Jobs: 1
Start Publishing: 2019-05-28
Stop Publishing: 2019-06-28
In-TAC Jay Ottawa, Canada
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         Perform SI analysis, measurement, and debug tasks in the development of advanced high density printed circuit board (PCB) for Infinera’s next generation coherent PIC (Photonic Integrated Circuit) and DSP modules

·         Design, simulate, analyze, and characterize electrical performance of the above electronic circuits

·         Write with clarity detailed HW specifications, SI simulation and measurement test plans, and test reports

·         Drive PCB placement and layout for robust SI performance

·         Design, layout, and characterize high speed Integrated SerDes circuits in various channel environments spanning multiple PCBs and high speed connectors

·         Evaluate SerDes interconnect PHY topologies, transmitter and receiver capabilities, parameter tuning, and related clocking / power supply considerations to meet critical performance and robustness objectives

·         Design with high emphasis on noise, jitter, and signal crosstalk suppression

·         Design with high emphasis on compact size/miniaturization appropriate for dense boards with multiple optical/electronic channels in parallel.

·         Drive supplier collaborations to optimize for SI performance.  Suppliers would include both external component vendors and internal (INFN ASICs).


        Expert level skill in Ansys HFSS EM analysis for 10-100GHz channels.

·         Deep understanding of transmission line theory

·         3+ years of direct experience with PCB and package geometry optimization with EM tools

·         Create PCB routing guideline based on the PCB geometry optimization and channel simulation.

·         Experience in high speed channel measurement with VNA and TDR, and the technique of de-embedding test fixture.

·         Experience in 28G+ SerDes design and debug, understanding of transmitter and receiver equalization, CDR behavior, modeling, and link training algorithms.

·         M.S. degree in electrical engineering or physics with minimum 5 years of industrial experience in signal integrity.


Preferred Experience and Qualification

·         Experience in defining PCB stack-up, material selection and trade-offs for 28G+ channels

·         Experience in SerDes channel simulation at 28Gbps data rate or higher with Keysight ADS or SiSoft QCD.

·         Experience in methodologies to achieve good correlation between simulation and measurement for PCB channels at 28G+.

·         Experience in component selection/evaluation for 28G+ SerDes including but not limited to SerDes IP, re-timer/repeater, connectors, DC blocking caps, and etc.

·         Experience in PCB design guideline for EMI. 

·         Experience in power integrity simulations and lab measurement verification

Experience in high speed backplane design desirable

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