Job Information
Sr. ASIC Design Engineer
In-TAC Jay Ottawa, Canada 8 Days Ago
Overview
Job Category: Computer/IT
Job Type: Full-Time
Posted: 2019-07-09
Requirements
Job Status
Start Publishing: 2019-07-09
Stop Publishing: 2019-09-09
In-TAC Jay Ottawa, Canada
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Description

What will you do:

Role overview :

    • This is an ASIC design position with the DSP ASIC team. Candidate will be involved in the design of large digital ASICs for fiber transmission systems typically working on a team with other designers and verification engineers.  

Why is this role important within Ciena? What impact can you expect to have?

    • DSP ASIC team designs and develops the core IP of the Ciena’s industry leading Wavelogic coherent engine Chipsets. Wavelogic ASICs are widely used in our products and they are one of the main contributors to our success.

What type of work environment will you be working in? Who are the key teams with whom you will interact?

    • As a digital ASIC designer in DSP ASIC team you will be working closely with the DSP systems team. You are expected to read and understand the DSP functional specifications and communicate and collaborate with DSP system designers. You are also expected to work closely with our ASIC verification team in various stages of verification of our IP.
Qualifications

What technical experience and/or professional and personal skills are required for this role?

    • Electrical engineering or computer science degree at the BASc or MASc level
    • Excellent grasp of System Verilog.
    • Extensive design knowledge.
    • C++ knowledge considered an asset
    • DSP design knowledge considered an asset
    • Expertise with digital design approaches and debug.
    • Ability to read and interpret DSP specifications.
    • Understanding of layout impacts and low power approaches is an asset.
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